top_module_phase2b Project Status (05/21/2012 - 15:32:49) | |||
Project File: | Phase2b.xise | Parser Errors: | No Errors |
Module Name: | top_module_phase2b | Implementation State: | Programming File Generated |
Target Device: | xc3s1000-5fg676 |
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No Errors |
Product Version: | ISE 13.3 |
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1554 Warnings (3 new) |
Design Goal: | Balanced |
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All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
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All Constraints Met |
Environment: | System Settings |
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0 (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Total Number Slice Registers | 9,269 | 15,360 | 60% | ||
Number used as Flip Flops | 9,267 | ||||
Number used as Latches | 2 | ||||
Number of 4 input LUTs | 10,685 | 15,360 | 69% | ||
Number of occupied Slices | 7,462 | 7,680 | 97% | ||
Number of Slices containing only related logic | 7,462 | 7,462 | 100% | ||
Number of Slices containing unrelated logic | 0 | 7,462 | 0% | ||
Total Number of 4 input LUTs | 11,342 | 15,360 | 73% | ||
Number used as logic | 10,685 | ||||
Number used as a route-thru | 657 | ||||
Number of bonded IOBs | 131 | 391 | 33% | ||
Number of RAMB16s | 4 | 24 | 16% | ||
Number of BUFGMUXs | 2 | 8 | 25% | ||
Number of DCMs | 1 | 4 | 25% | ||
Average Fanout of Non-Clock Nets | 3.86 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Thu 13. Sep 22:50:17 2012 | 0 | 1545 Warnings (1 new) | 67 Infos (0 new) | |
Translation Report | Current | Thu 13. Sep 22:50:28 2012 | 0 | 0 | 1 Info (0 new) | |
Map Report | Current | Thu 13. Sep 22:53:21 2012 | 0 | 2 Warnings (0 new) | 6 Infos (0 new) | |
Place and Route Report | Current | Thu 13. Sep 22:54:24 2012 | 0 | 6 Warnings (2 new) | 0 | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | Thu 13. Sep 22:54:39 2012 | 0 | 0 | 4 Infos (0 new) | |
Bitgen Report | Current | Thu 13. Sep 22:55:20 2012 | 0 | 1 Warning (0 new) | 1 Info (0 new) |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Current | Thu 13. Sep 22:55:22 2012 | |
WebTalk Log File | Current | Thu 13. Sep 22:55:28 2012 |