Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:13.3 (WebPack) - O.76xd Target Family: Spartan3
OS Platform: NT64 Target Device: xc3s1000
Project ID (random number) c055a6224bfb4a0d8141213360f93361.17664867B04049DEB7CD1D2F6D87BA78.43 Target Package: fg676
Registration ID 201174391_0_0_613 Target Speed: -5
Date Generated 2012-09-13T22:55:22 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i5-2410M CPU @ 2.30GHz CPU Speed 2294 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=107
  • 12-bit adder=1
  • 14-bit adder=1
  • 15-bit adder=1
  • 16-bit adder=3
  • 18-bit adder=5
  • 19-bit adder=1
  • 2-bit adder=48
  • 20-bit adder=4
  • 21-bit adder=1
  • 24-bit adder=2
  • 28-bit adder=1
  • 3-bit adder=2
  • 31-bit adder=1
  • 32-bit adder=5
  • 32-bit subtractor=3
  • 6-bit adder=1
  • 6-bit addsub=1
  • 6-bit subtractor=1
  • 8-bit adder=6
  • 8-bit subtractor=11
  • 9-bit adder=6
  • 9-bit addsub=1
  • 9-bit subtractor=1
Comparators=123
  • 12-bit comparator greatequal=1
  • 16-bit comparator greatequal=1
  • 16-bit comparator greater=3
  • 16-bit comparator less=5
  • 17-bit comparator greatequal=1
  • 17-bit comparator less=1
  • 18-bit comparator greatequal=5
  • 19-bit comparator greatequal=1
  • 2-bit comparator equal=48
  • 20-bit comparator greatequal=4
  • 21-bit comparator greatequal=1
  • 24-bit comparator greatequal=1
  • 28-bit comparator greatequal=1
  • 3-bit comparator equal=2
  • 31-bit comparator equal=1
  • 32-bit comparator greatequal=2
  • 32-bit comparator greater=5
  • 32-bit comparator less=4
  • 32-bit comparator not equal=1
  • 6-bit comparator equal=1
  • 6-bit comparator greatequal=1
  • 6-bit comparator greater=1
  • 6-bit comparator less=1
  • 7-bit comparator greatequal=1
  • 7-bit comparator less=1
  • 8-bit comparator equal=1
  • 8-bit comparator greatequal=1
  • 8-bit comparator greater=9
  • 8-bit comparator less=2
  • 8-bit comparator not equal=3
  • 9-bit comparator equal=2
  • 9-bit comparator greatequal=3
  • 9-bit comparator greater=1
  • 9-bit comparator less=4
  • 9-bit comparator lessequal=1
  • 9-bit comparator not equal=2
Counters=11
  • 16-bit up counter=2
  • 20-bit down counter=3
  • 3-bit up counter=1
  • 30-bit down counter=1
  • 4-bit up counter=1
  • 5-bit up counter=1
  • 7-bit up counter=1
  • 9-bit updown counter=1
FSMs=31 Latches=5
  • 8-bit latch=5
Multiplexers=198
  • 1-bit 4-to-1 multiplexer=66
  • 2-bit 4-to-1 multiplexer=52
  • 24-bit 4-to-1 multiplexer=1
  • 3-bit 4-to-1 multiplexer=2
  • 32-bit 4-to-1 multiplexer=72
  • 8-bit 4-to-1 multiplexer=3
  • 8-bit 71-to-1 multiplexer=1
  • 8-bit 8-to-1 multiplexer=1
RAMs=2
  • 512x16-bit single-port block RAM=2
ROMs=3
  • 16x6-bit ROM=2
  • 64x4-bit ROM=1
Registers=9333
  • Flip-Flops=9333
Xors=85
  • 1-bit xor2=84
  • 1-bit xor3=1
MiscellaneousStatistics
  • AGG_BONDED_IO=131
  • AGG_IO=131
  • AGG_SLICE=7462
  • NUM_4_INPUT_LUT=11342
  • NUM_BONDED_IOB=131
  • NUM_BUFGMUX=2
  • NUM_CYMUX=1603
  • NUM_DCM=1
  • NUM_LUT_RT=657
  • NUM_RAMB16=4
  • NUM_SLICEL=7456
  • NUM_SLICEM=6
  • NUM_SLICE_FF=9267
  • NUM_SLICE_LATCH=2
  • NUM_XOR=841
  • Xilinx Core fifo_generator_v4_2, Coregen 9.2.04i_ip2=2
NetStatistics
  • NumNets_Active=14451
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=56
  • NumNodesOfType_Active_BRAMDUMMY=48
  • NumNodesOfType_Active_CLKPIN=7108
  • NumNodesOfType_Active_CNTRLPIN=12910
  • NumNodesOfType_Active_DOUBLE=27823
  • NumNodesOfType_Active_DUMMY=33198
  • NumNodesOfType_Active_DUMMYBANK=47
  • NumNodesOfType_Active_DUMMYESC=40
  • NumNodesOfType_Active_GLOBAL=348
  • NumNodesOfType_Active_HFULLHEX=380
  • NumNodesOfType_Active_HLONG=104
  • NumNodesOfType_Active_HUNIHEX=1212
  • NumNodesOfType_Active_INPUT=38648
  • NumNodesOfType_Active_IOBOUTPUT=39
  • NumNodesOfType_Active_OMUX=16988
  • NumNodesOfType_Active_OUTPUT=14321
  • NumNodesOfType_Active_PREBXBY=10517
  • NumNodesOfType_Active_VFULLHEX=2857
  • NumNodesOfType_Active_VLONG=847
  • NumNodesOfType_Active_VUNIHEX=983
  • NumNodesOfType_Gnd_BRAMADDR=2
  • NumNodesOfType_Gnd_BRAMDUMMY=6
  • NumNodesOfType_Gnd_CNTRLPIN=10
  • NumNodesOfType_Gnd_DOUBLE=30
  • NumNodesOfType_Gnd_DUMMYBANK=4
  • NumNodesOfType_Gnd_HUNIHEX=1
  • NumNodesOfType_Gnd_INPUT=59
  • NumNodesOfType_Gnd_OMUX=49
  • NumNodesOfType_Gnd_OUTPUT=43
  • NumNodesOfType_Gnd_PREBXBY=58
  • NumNodesOfType_Gnd_VFULLHEX=3
SiteStatistics
  • IOB-DIFFM=65
  • IOB-DIFFS=66
  • SLICEL-SLICEM=3741
SiteSummary
  • BUFGMUX=2
  • BUFGMUX_GCLKMUX=2
  • BUFGMUX_GCLK_BUFFER=2
  • DCM=1
  • DCM_DCM=1
  • IOB=131
  • IOB_INBUF=41
  • IOB_OUTBUF=106
  • IOB_PAD=131
  • RAMB16=4
  • RAMB16_RAMB16=4
  • RAMB16_RAMB16A=4
  • RAMB16_RAMB16B=2
  • SLICEL=7456
  • SLICEL_C1VDD=124
  • SLICEL_C2VDD=115
  • SLICEL_CYMUXF=831
  • SLICEL_CYMUXG=772
  • SLICEL_F=5031
  • SLICEL_F5MUX=870
  • SLICEL_F6MUX=9
  • SLICEL_FFX=3268
  • SLICEL_FFY=6001
  • SLICEL_G=6299
  • SLICEL_GNDF=407
  • SLICEL_GNDG=359
  • SLICEL_XORF=425
  • SLICEL_XORG=416
  • SLICEM=6
  • SLICEM_F=6
  • SLICEM_F5MUX=6
  • SLICEM_F6MUX=6
  • SLICEM_G=6
 
Configuration Data
BUFGMUX
  • S=[S_INV:2] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:2]
  • S=[S_INV:2] [S:0]
DCM
  • PSCLK=[PSCLK_INV:1] [PSCLK:0]
  • PSEN=[PSEN_INV:1] [PSEN:0]
  • PSINCDEC=[PSINCDEC:0] [PSINCDEC_INV:1]
  • RST=[RST:0] [RST_INV:1]
DCM_DCM
  • CLKDV_DIVIDE=[2:1]
  • CLKOUT_PHASE_SHIFT=[NONE:1]
  • CLK_FEEDBACK=[1X:1]
  • DESKEW_ADJUST=[8:1]
  • DFS_FREQUENCY_MODE=[LOW:1]
  • DLL_FREQUENCY_MODE=[LOW:1]
  • DUTY_CYCLE_CORRECTION=[TRUE:1]
  • FACTORY_JF1=[0XC0:1]
  • FACTORY_JF2=[0X80:1]
  • PSCLK=[PSCLK_INV:1] [PSCLK:0]
  • PSEN=[PSEN_INV:1] [PSEN:0]
  • PSINCDEC=[PSINCDEC:0] [PSINCDEC_INV:1]
  • RST=[RST:0] [RST_INV:1]
IOB
  • O1=[O1_INV:2] [O1:104]
  • T1=[T1_INV:0] [T1:16]
IOB_OUTBUF
  • IN=[IN_INV:2] [IN:104]
  • TRI=[TRI_INV:0] [TRI:16]
IOB_PAD
  • DRIVEATTRBOX=[4:25] [8:80] [12:1]
  • IOATTRBOX=[LVCMOS33:131]
  • PULL=[PULLUP:15]
  • SLEW=[SLOW:105] [FAST:1]
RAMB16
  • CLKA=[CLKA_INV:0] [CLKA:4]
  • CLKB=[CLKB_INV:0] [CLKB:2]
  • ENA=[ENA_INV:0] [ENA:4]
  • ENB=[ENB_INV:0] [ENB:2]
  • SSRA=[SSRA_INV:0] [SSRA:4]
  • SSRB=[SSRB_INV:0] [SSRB:2]
  • WEA=[WEA:4] [WEA_INV:0]
  • WEB=[WEB:2] [WEB_INV:0]
RAMB16_RAMB16A
  • CLKA=[CLKA_INV:0] [CLKA:4]
  • ENA=[ENA_INV:0] [ENA:4]
  • PORTA_ATTR=[1024X18:4]
  • SSRA=[SSRA_INV:0] [SSRA:4]
  • WEA=[WEA:4] [WEA_INV:0]
  • WRITEMODEA=[WRITE_FIRST:4]
RAMB16_RAMB16B
  • CLKB=[CLKB_INV:0] [CLKB:2]
  • ENB=[ENB_INV:0] [ENB:2]
  • PORTB_ATTR=[512X36:2]
  • SSRB=[SSRB_INV:0] [SSRB:2]
  • WEB=[WEB:2] [WEB_INV:0]
  • WRITEMODEB=[WRITE_FIRST:2]
SLICEL
  • BX=[BX_INV:0] [BX:1674]
  • BY=[BY:2963] [BY_INV:17]
  • CE=[CE:5787] [CE_INV:62]
  • CIN=[CIN_INV:0] [CIN:732]
  • CLK=[CLK:7098] [CLK_INV:2]
  • SR=[SR:6964] [SR_INV:18]
SLICEL_CYMUXF
  • 0=[0:831] [0_INV:0]
  • 1=[1_INV:0] [1:831]
SLICEL_CYMUXG
  • 0=[0:772] [0_INV:0]
SLICEL_F5MUX
  • S0=[S0:870] [S0_INV:0]
SLICEL_F6MUX
  • S0=[S0:9] [S0_INV:0]
SLICEL_FFX
  • CE=[CE:2232] [CE_INV:47]
  • CK=[CK:3268] [CK_INV:0]
  • D=[D:3268] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:3217] [INIT1:51]
  • FFX_SR_ATTR=[SRLOW:3205] [SRHIGH:63]
  • LATCH_OR_FF=[FF:3268]
  • SR=[SR:3163] [SR_INV:16]
  • SYNC_ATTR=[ASYNC:3268]
SLICEL_FFY
  • CE=[CE:5214] [CE_INV:57]
  • CK=[CK:5999] [CK_INV:2]
  • D=[D:5984] [D_INV:17]
  • FFY_INIT_ATTR=[INIT0:5963] [INIT1:38]
  • FFY_SR_ATTR=[SRLOW:5939] [SRHIGH:62]
  • LATCH_OR_FF=[FF:5999] [LATCH:2]
  • REV=[REV_INV:0] [REV:18]
  • SR=[SR:5910] [SR_INV:18]
  • SYNC_ATTR=[ASYNC:6001]
SLICEL_XORF
  • 1=[1_INV:0] [1:425]
SLICEM
  • BX=[BX_INV:0] [BX:6]
  • BY=[BY:6] [BY_INV:0]
SLICEM_F
  • LUT_OR_MEM=[LUT:6]
SLICEM_F5MUX
  • S0=[S0:6] [S0_INV:0]
SLICEM_F6MUX
  • S0=[S0:6] [S0_INV:0]
SLICEM_G
  • LUT_OR_MEM=[LUT:6]
 
Pin Data
BUFGMUX
  • I0=2
  • O=2
  • S=2
BUFGMUX_GCLKMUX
  • I0=2
  • OUT=2
  • S=2
BUFGMUX_GCLK_BUFFER
  • IN=2
  • OUT=2
DCM
  • CLK0=1
  • CLK90=1
  • CLKFB=1
  • CLKIN=1
  • LOCKED=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
DCM_DCM
  • CLK0=1
  • CLK90=1
  • CLKFB=1
  • CLKIN=1
  • LOCKED=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
IOB
  • I=41
  • O1=106
  • PAD=131
  • T1=16
IOB_INBUF
  • IN=41
  • OUT=41
IOB_OUTBUF
  • IN=106
  • OUT=106
  • TRI=16
IOB_PAD
  • PAD=131
RAMB16
  • ADDRA10=4
  • ADDRA11=4
  • ADDRA12=4
  • ADDRA13=4
  • ADDRA4=4
  • ADDRA5=4
  • ADDRA6=4
  • ADDRA7=4
  • ADDRA8=4
  • ADDRA9=4
  • ADDRB10=2
  • ADDRB11=2
  • ADDRB12=2
  • ADDRB13=2
  • ADDRB5=2
  • ADDRB6=2
  • ADDRB7=2
  • ADDRB8=2
  • ADDRB9=2
  • CLKA=4
  • CLKB=2
  • DIA0=1
  • DIA1=1
  • DIA10=1
  • DIA11=1
  • DIA12=1
  • DIA13=1
  • DIA14=1
  • DIA15=1
  • DIA2=1
  • DIA3=1
  • DIA4=1
  • DIA5=1
  • DIA6=1
  • DIA7=1
  • DIA8=1
  • DIA9=1
  • DIB0=1
  • DIB1=1
  • DIB10=1
  • DIB11=1
  • DIB12=1
  • DIB13=1
  • DIB14=1
  • DIB15=1
  • DIB16=1
  • DIB17=1
  • DIB18=1
  • DIB19=1
  • DIB2=1
  • DIB20=1
  • DIB21=1
  • DIB22=1
  • DIB23=1
  • DIB24=1
  • DIB25=1
  • DIB26=1
  • DIB27=1
  • DIB28=1
  • DIB29=1
  • DIB3=1
  • DIB30=1
  • DIB31=1
  • DIB4=1
  • DIB5=1
  • DIB6=1
  • DIB7=1
  • DIB8=1
  • DIB9=1
  • DIPA0=1
  • DIPA1=1
  • DIPB0=1
  • DIPB1=1
  • DIPB2=1
  • DIPB3=1
  • DOA0=3
  • DOA1=3
  • DOA10=3
  • DOA11=3
  • DOA12=3
  • DOA13=3
  • DOA14=3
  • DOA15=3
  • DOA2=3
  • DOA3=3
  • DOA4=3
  • DOA5=3
  • DOA6=1
  • DOA7=1
  • DOA8=3
  • DOA9=3
  • DOB0=1
  • DOB1=1
  • DOB10=1
  • DOB11=1
  • DOB12=1
  • DOB13=1
  • DOB14=1
  • DOB15=1
  • DOB16=1
  • DOB17=1
  • DOB18=1
  • DOB19=1
  • DOB2=1
  • DOB20=1
  • DOB21=1
  • DOB22=1
  • DOB23=1
  • DOB24=1
  • DOB25=1
  • DOB26=1
  • DOB27=1
  • DOB28=1
  • DOB29=1
  • DOB3=1
  • DOB30=1
  • DOB31=1
  • DOB4=1
  • DOB5=1
  • DOB6=1
  • DOB7=1
  • DOB8=1
  • DOB9=1
  • ENA=4
  • ENB=2
  • SSRA=4
  • SSRB=2
  • WEA=4
  • WEB=2
RAMB16_RAMB16
  • ADDRA=4
  • ADDRB=2
  • DIA=4
  • DIB=2
  • DOA=4
  • DOB=2
RAMB16_RAMB16A
  • ADDRA=4
  • ADDRA10=4
  • ADDRA11=4
  • ADDRA12=4
  • ADDRA13=4
  • ADDRA4=4
  • ADDRA5=4
  • ADDRA6=4
  • ADDRA7=4
  • ADDRA8=4
  • ADDRA9=4
  • CLKA=4
  • DIA=4
  • DIA0=1
  • DIA1=1
  • DIA10=1
  • DIA11=1
  • DIA12=1
  • DIA13=1
  • DIA14=1
  • DIA15=1
  • DIA2=1
  • DIA3=1
  • DIA4=1
  • DIA5=1
  • DIA6=1
  • DIA7=1
  • DIA8=1
  • DIA9=1
  • DIPA0=1
  • DIPA1=1
  • DOA=4
  • DOA0=3
  • DOA1=3
  • DOA10=3
  • DOA11=3
  • DOA12=3
  • DOA13=3
  • DOA14=3
  • DOA15=3
  • DOA2=3
  • DOA3=3
  • DOA4=3
  • DOA5=3
  • DOA6=1
  • DOA7=1
  • DOA8=3
  • DOA9=3
  • ENA=4
  • SSRA=4
  • WEA=4
RAMB16_RAMB16B
  • ADDRB=2
  • ADDRB10=2
  • ADDRB11=2
  • ADDRB12=2
  • ADDRB13=2
  • ADDRB5=2
  • ADDRB6=2
  • ADDRB7=2
  • ADDRB8=2
  • ADDRB9=2
  • CLKB=2
  • DIB=2
  • DIB0=1
  • DIB1=1
  • DIB10=1
  • DIB11=1
  • DIB12=1
  • DIB13=1
  • DIB14=1
  • DIB15=1
  • DIB16=1
  • DIB17=1
  • DIB18=1
  • DIB19=1
  • DIB2=1
  • DIB20=1
  • DIB21=1
  • DIB22=1
  • DIB23=1
  • DIB24=1
  • DIB25=1
  • DIB26=1
  • DIB27=1
  • DIB28=1
  • DIB29=1
  • DIB3=1
  • DIB30=1
  • DIB31=1
  • DIB4=1
  • DIB5=1
  • DIB6=1
  • DIB7=1
  • DIB8=1
  • DIB9=1
  • DIPB0=1
  • DIPB1=1
  • DIPB2=1
  • DIPB3=1
  • DOB=2
  • DOB0=1
  • DOB1=1
  • DOB10=1
  • DOB11=1
  • DOB12=1
  • DOB13=1
  • DOB14=1
  • DOB15=1
  • DOB16=1
  • DOB17=1
  • DOB18=1
  • DOB19=1
  • DOB2=1
  • DOB20=1
  • DOB21=1
  • DOB22=1
  • DOB23=1
  • DOB24=1
  • DOB25=1
  • DOB26=1
  • DOB27=1
  • DOB28=1
  • DOB29=1
  • DOB3=1
  • DOB30=1
  • DOB31=1
  • DOB4=1
  • DOB5=1
  • DOB6=1
  • DOB7=1
  • DOB8=1
  • DOB9=1
  • ENB=2
  • SSRB=2
  • WEB=2
SLICEL
  • BX=1674
  • BY=2980
  • CE=5849
  • CIN=732
  • CLK=7100
  • COUT=772
  • F1=5017
  • F2=4617
  • F3=3090
  • F4=2159
  • F5=19
  • FX=3
  • FXINA=9
  • FXINB=9
  • G1=6296
  • G2=5888
  • G3=3562
  • G4=2522
  • SR=6982
  • X=2061
  • XB=26
  • XQ=3268
  • Y=2036
  • YQ=6001
SLICEL_C1VDD
  • 1=124
SLICEL_C2VDD
  • 1=115
SLICEL_CYMUXF
  • 0=831
  • 1=831
  • OUT=831
  • S0=831
SLICEL_CYMUXG
  • 0=772
  • 1=772
  • OUT=772
  • S0=772
SLICEL_F
  • A1=5017
  • A2=4617
  • A3=3090
  • A4=2159
  • D=5031
SLICEL_F5MUX
  • F=868
  • G=870
  • OUT=870
  • S0=870
SLICEL_F6MUX
  • 0=9
  • 1=9
  • OUT=9
  • S0=9
SLICEL_FFX
  • CE=2279
  • CK=3268
  • D=3268
  • Q=3268
  • SR=3179
SLICEL_FFY
  • CE=5271
  • CK=6001
  • D=6001
  • Q=6001
  • REV=18
  • SR=5928
SLICEL_G
  • A1=6296
  • A2=5888
  • A3=3562
  • A4=2522
  • D=6299
SLICEL_GNDF
  • 0=407
SLICEL_GNDG
  • 0=359
SLICEL_XORF
  • 0=425
  • 1=425
  • O=425
SLICEL_XORG
  • 0=416
  • 1=416
  • O=416
SLICEM
  • BX=6
  • BY=6
  • F1=6
  • F2=6
  • F3=5
  • F4=4
  • F5=6
  • FX=3
  • FXINA=6
  • FXINB=6
  • G1=6
  • G2=6
  • G3=5
  • G4=3
  • Y=3
SLICEM_F
  • A1=6
  • A2=6
  • A3=5
  • A4=4
  • D=6
SLICEM_F5MUX
  • F=6
  • G=6
  • OUT=6
  • S0=6
SLICEM_F6MUX
  • 0=6
  • 1=6
  • OUT=6
  • S0=6
SLICEM_G
  • A1=6
  • A2=6
  • A3=5
  • A4=3
  • D=6
 
Tool Usage
Command Line History
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -aul -nt timestamp -uc <fname>.ucf -p xc3s1000-fg676-5 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc3s1000-fg676-5 -timing -logic_opt off -ol high -xe n -t 1 -register_duplication off -cm area -ir off -pr off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -aul -nt timestamp -uc <fname>.ucf -p xc3s1000-fg676-5 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc3s1000-fg676-5 -timing -logic_opt off -ol high -xe n -t 1 -register_duplication off -cm area -ir off -pr off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -aul -nt timestamp -uc <fname>.ucf -p xc3s1000-fg676-5 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc3s1000-fg676-5 -timing -logic_opt off -ol high -xe n -t 1 -register_duplication off -cm area -ir off -pr off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -aul -nt timestamp -uc <fname>.ucf -p xc3s1000-fg676-5 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc3s1000-fg676-5 -timing -logic_opt off -ol high -xe n -t 1 -register_duplication off -cm area -ir off -pr off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -aul -nt timestamp -uc <fname>.ucf -p xc3s1000-fg676-5 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc3s1000-fg676-5 -timing -logic_opt off -ol high -xe n -t 1 -register_duplication off -cm area -ir off -pr off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -aul -nt timestamp -uc <fname>.ucf -p xc3s1000-fg676-5 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc3s1000-fg676-5 -timing -logic_opt off -ol high -xe n -t 1 -register_duplication off -cm area -ir off -pr off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -aul -nt timestamp -uc <fname>.ucf -p xc3s1000-fg676-5 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc3s1000-fg676-5 -timing -logic_opt off -ol high -xe n -t 1 -register_duplication off -cm area -ir off -pr off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -filter <ise_file>
  • ngdbuild -filter <ise_file> -intstyle ise -dd _ngo -sd <dname> -aul -nt timestamp -uc <fname>.ucf -p xc3s1000-fg676-5 <fname>.ngc <fname>.ngd
  • map -filter <ise_file> -intstyle ise -p xc3s1000-fg676-5 -timing -logic_opt off -ol high -xe n -t 1 -register_duplication off -cm area -ir off -pr off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -filter <ise_file> -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -filter <fname>.filter -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -filter <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 11 8 0 0 0 0 0
arwz 23 23 0 0 0 0 0
bitgen 24 24 0 0 0 0 0
map 29 29 0 0 0 0 0
netgen 3 3 0 0 0 0 0
ngcbuild 2 2 0 0 0 0 0
ngdbuild 32 32 0 0 0 0 0
par 30 27 3 0 0 0 0
trce 27 27 0 0 0 0 0
xawinfo 1 1 0 0 0 0 0
xst 129 129 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/dsm_c_design_summary_overview.htm ( 1 ) /doc/usenglish/isehelp/ise_c_implementation_results_overview.htm ( 1 )
/doc/usenglish/isehelp/ise_c_simulation_timing.htm ( 1 ) /doc/usenglish/isehelp/ise_c_timing_analysis_cross_probing.htm ( 1 )
/doc/usenglish/isehelp/ise_c_timing_analysis_exceptions.htm ( 1 ) /doc/usenglish/isehelp/ise_c_timing_analysis_unconstrained_paths.htm ( 1 )
/doc/usenglish/isehelp/ite_c_overview.htm ( 1 ) /doc/usenglish/isehelp/plugin_ism.pdf ( 1 )
/doc/usenglish/isehelp/pta_c_overview.htm ( 1 ) /doc/usenglish/isehelp/pta_p_ttc-timing-report-view.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=true PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store non-default values only
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2012-03-14T08:41:23
PROP_intWbtProjectID=17664867B04049DEB7CD1D2F6D87BA78 PROP_intWbtProjectIteration=43
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_xilxMapTimingDrivenPacking=true PROP_xilxNgdbld_AUL=true
PROP_AutoTop=true PROP_DevFamily=Spartan3
PROP_DevDevice=xc3s1000 PROP_DevFamilyPMName=spartan3
PROP_MapExtraEffort=Normal PROP_DevPackage=fg676
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-5
PROP_PreferredLanguage=VHDL FILE_NGC=3
FILE_UCF=1 FILE_VHDL=56
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_DCM=1 NGDBUILD_NUM_FD=10 NGDBUILD_NUM_FDC=1615
NGDBUILD_NUM_FDCE=7348 NGDBUILD_NUM_FDCP=17 NGDBUILD_NUM_FDCPE=9 NGDBUILD_NUM_FDE=150
NGDBUILD_NUM_FDP=79 NGDBUILD_NUM_FDPE=43 NGDBUILD_NUM_GND=3 NGDBUILD_NUM_IBUF=22
NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=173 NGDBUILD_NUM_IOBUF=16 NGDBUILD_NUM_LD=2
NGDBUILD_NUM_LUT1=630 NGDBUILD_NUM_LUT2=3803 NGDBUILD_NUM_LUT2_D=25 NGDBUILD_NUM_LUT2_L=16
NGDBUILD_NUM_LUT3=1932 NGDBUILD_NUM_LUT3_D=38 NGDBUILD_NUM_LUT3_L=27 NGDBUILD_NUM_LUT4=4546
NGDBUILD_NUM_LUT4_D=64 NGDBUILD_NUM_LUT4_L=70 NGDBUILD_NUM_MUXCY=1603 NGDBUILD_NUM_MUXF5=874
NGDBUILD_NUM_MUXF6=12 NGDBUILD_NUM_MUXF7=3 NGDBUILD_NUM_OBUF=90 NGDBUILD_NUM_RAMB16_S18_S36=2
NGDBUILD_NUM_VCC=3 NGDBUILD_NUM_XORCY=841
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_DCM=1 NGDBUILD_NUM_FD=10 NGDBUILD_NUM_FDC=1615
NGDBUILD_NUM_FDCE=7348 NGDBUILD_NUM_FDCP=17 NGDBUILD_NUM_FDCPE=9 NGDBUILD_NUM_FDE=150
NGDBUILD_NUM_FDP=79 NGDBUILD_NUM_FDPE=43 NGDBUILD_NUM_GND=5 NGDBUILD_NUM_IBUF=40
NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=173 NGDBUILD_NUM_LD=2 NGDBUILD_NUM_LUT1=630
NGDBUILD_NUM_LUT2=3803 NGDBUILD_NUM_LUT2_D=25 NGDBUILD_NUM_LUT2_L=16 NGDBUILD_NUM_LUT3=1932
NGDBUILD_NUM_LUT3_D=38 NGDBUILD_NUM_LUT3_L=27 NGDBUILD_NUM_LUT4=4546 NGDBUILD_NUM_LUT4_D=64
NGDBUILD_NUM_LUT4_L=70 NGDBUILD_NUM_MUXCY=1603 NGDBUILD_NUM_MUXF5=874 NGDBUILD_NUM_MUXF6=12
NGDBUILD_NUM_MUXF7=3 NGDBUILD_NUM_OBUF=90 NGDBUILD_NUM_OBUFT=16 NGDBUILD_NUM_PULLUP=15
NGDBUILD_NUM_RAMB16_S18=2 NGDBUILD_NUM_RAMB16_S18_S36=2 NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=5
NGDBUILD_NUM_XORCY=841
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s1000-5-fg676 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -sd=<No customer specific name> -write_timing_constraints=NO
-cross_clock_analysis=NO -bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100
-verilog2001=YES -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -mult_style=Auto -iobuf=YES -max_fanout=500
-bufg=8 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Yes -use_sync_set=Yes -use_sync_reset=Yes -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5