main Project Status (01/30/2012 - 13:44:47)
Project File: imperial_daqtest.xise Parser Errors: No Errors
Module Name: main Implementation State: Programming File Generated
Target Device: xc3s1000-5fg676
  • Errors:
No Errors
Product Version:ISE 13.3
  • Warnings:
18 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 57 15,360 1%  
Number of 4 input LUTs 73 15,360 1%  
Number of occupied Slices 61 7,680 1%  
    Number of Slices containing only related logic 61 61 100%  
    Number of Slices containing unrelated logic 0 61 0%  
Total Number of 4 input LUTs 73 15,360 1%  
Number of bonded IOBs 61 391 15%  
Number of BUFGMUXs 1 8 12%  
Average Fanout of Non-Clock Nets 3.07      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon 30. Jan 13:28:26 201202 Warnings (0 new)0
Translation ReportCurrentMon 30. Jan 13:43:26 2012016 Warnings (0 new)64 Infos (0 new)
Map ReportCurrentMon 30. Jan 13:43:30 2012003 Infos (0 new)
Place and Route ReportCurrentMon 30. Jan 13:43:38 2012001 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentMon 30. Jan 13:43:41 2012004 Infos (0 new)
Bitgen ReportCurrentMon 30. Jan 13:43:48 2012001 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentMon 30. Jan 14:03:38 2012
WebTalk ReportCurrentMon 30. Jan 13:43:48 2012
WebTalk Log FileCurrentMon 30. Jan 13:44:47 2012

Date Generated: 01/30/2012 - 14:07:42